system resets can occur due to hard reset (hardware reset)
or soft reset (software reset). The DAC (digital-to-analog
converter) outputs are disabled
after both Hard Reset and Soft Reset events.
monitor reset scheme.
resets are caused by:
voltage conditions on either 5V, +15V or -15V, +12V or -12V,
reset via the host (through Interface
CPLD), or watchdog timeout
reset line (TTL) activation (one dedicated input per board)
reset occurs 400ms after power-on or fail events, and 200ms
after software reset or external reset events. The Hard Reset
lasts 200-400 msec, leaving the DACs with Vout switched away
from the DAC and tied to the DAC's analog ground. The first
write from the SHARC to the DAC will cause this switch (Vout)
to shift back to the DAC for normal operations.
resets are caused by a watchdog timeout from the DSP's flag
output, or when the host writes a key sequence to the host
system registers. External reset is triggered using an external
TTL input. Both software and external resets are active low.
To guarantee reset when Vcc is low, the triple OR gate will
operate down to Vcc = +1V.
software reset is handled by a Watchdog
Timer with an adjustable timeout. The Watchdog Timer is
intended to catch malfunctioning firmware. The Watchdog Timer
does not monitor Vcc. The timer only responds to a timeout
accompanied by a 200 ms reset. The Watchdog Timer is disabled
during power-up, and following a reset of the SHARC DSP, allows
the DSP to boot and begin instruction execution.
Soft Reset will:
all analog command outputs to switch away from the DAC to
a low impedance path (to their associated analog ground).
reset the motion blocks, causing them to clear dedicated
I/O to their DSP-configured default state, and to reset
the position counters and associated registers. Soft Reset
will not enable the FPGA configuration to be reloaded. Note
that it takes a power-on Hard Reset to cause the FPGAs to
the host interface Reset Status register and all other host
reset the SHARC DSP. The host driver will soft-boot the
the Soft Reset watchdog circuitry, a latched reset is used,
which provides an added protection of not allowing a malfunctioning
SHARC DSP to mistakenly write to the DAC (the Soft Reset is
held until the host clears it, as part of the host's watchdog
timeout recovery routine).
Fail Control of DAC Outputs
DAC has embedded analog switches in the output stage. The
analog switches G1 and G2 are controlled by the on-chip voltage
monitor and by the dedicated reset input pin (Reset IN). A
low voltage on the Reset IN input will cause G1 to open and
G2 to close, clamping Vout to AGnd via a low impedance path
(typically 1K ohms). This condition will remain until the
reset input goes high and a valid word is written into the
Reset IN input is the active low OR'ed condition of Hard
Reset or Soft Reset.
65K ohm resistor from Vout to AGnd will maintain 0 volts
on Vout until the supplies reach +1 volt. What happens if
we lose an analog power rail? The Reset IN input will go
low once one of our rails crosses the reset threshold. The
Reset IN input is valid for Vdd and Vss to +1.2 volts, and
below those voltage levels, the 65K ohm pulldown resistor
protects the circuit.