Analog Inputs

Analog signals, from such external devices as optical sensors and LVDTs, can be fed to the XMP controller. They are wired through dedicated analog lines (e.g., ANALOG_IN_0+ and _0-), then converted to digital values by the XMP controller's analog-digital converter (ADC). The ADC used in XMP controllers is an Analog Devices 16-bit AD976A.

The figure below outlines the analog input subsystem for the XMP controller.

The XMP controller accepts analog inputs having a maximum dynamic range of +10V or -10V, and converts these to 16-bit digital values within the ADC. 17 kHz noise filtering at the inputs removes unwanted voltage spikes. Because the highest digital resolution is attained when analog inputs are scaled to 10V, it is advantageous to rescale lower voltage inputs via the integrated programmable gain amplifier (PGA). Gain factors are individually selectable at gain select = 1, 2, 4, and 8, for ±10V, ±5V, ±2.5V, and ±1.25V inputs, respectively.

The multiplexer provides fault protection as well as channel selection. With no power applied, the switches are OFF. Overvoltage clamps become activated at ±13.5V.

ADC Subsystem Specifications
Max. Input Voltage	± 10V
Input Ranges	± 1.25V; ± 2.5V; ± 10V; or, ± (%)V
Resolution	16 bits
Channels	8
Input Impedance	100k
Signal Bandwidth	DC - 17 kHz
Conversion Time	10µs
Conversion Rate	Once per servo cycle (8 channels)1
DC Offset	15mV (max.) on 10V range.
Gain Uncertainty	0.5% (max.) on 10V range.
Nonlinearity	6 LSB

1. Please note that ADC conversion rates vary slightly, depending upon where within the servo cycle an analog change occurs. If an analog input changes near the end of the cycle, the digital conversion may occur sooner after the change than if the change occurs at the very beginning of the servo cycle.

XMP Controller Systems and Subsystems

Main Board and Expansion Board

Each XMP controller contains one main control board, capable of operating up to eight (8) axes. The main board contains the SHARC DSP, which processes all data between the host computer and motion hardware. In addition, one optional expansion board may be connected to a main board to add up to eight (8) more axes. Unlike main boards, expansion boards do NOT have their own SHARC DSP; they rely on the main board's SHARC DSP to do all digital processing.

Motion Block

Each main and expansion board has two (2) "motion blocks." Each motion block, in turn, contains four (4) "motor blocks," each of which controls one motor (see "Motor Block" below). Because motion blocks contain multiple motor blocks and are linked to all other motion blocks on the controller, it is possible to freely map one object to another. This provides the XMP controller with unprecedented flexibility and speed in coordinated motion.

A motion block is not a single piece of hardware, but actually consists of one field programmable gate array (FPGA), plus other hardware components. It is useful to think in terms of motion blocks to best understand how the XMP controller works. The motion block serves as the interface between the SHARC processor subsystem and motion I/O signals, and handles the interface to output peripherals (DACs, XCVRs, and opto-I/O), as well as the interface to feedback peripherals. Each motion block subsystem has a high speed serial interface to the SHARC DSP subsystem.

Motor Block

Contained within each motion block are four (4) "motor blocks." Motor blocks represent the most basic unit of motion control within the XMP environment. Each motor block acts as a dedicated gateway between the host computer and motion control components such as motors and encoders.

List of Figures

The next three pages illustrate overall data flow and component architecture of a typical XMP controller, including:

See Overall architecture: main and expansion boards below.
See Motion block detail below.
See Motor block detail below.

A study of these figures will provide some insight into an XMP controller's component layout and data flow.

Overall architecture: main and expansion boards.

Motion block detail.

Motor block detail.

DAC Circuitry

The D/A converters are 16-bit and DC-specified for high performance.

DAC circuitry.

Four pairs of DACs (eight total) are associated with each motion block. The first DAC of the pair is the Servo Command Output DAC, the second is an Auxiliary DAC for optional two-phase sinusoidal commutation support. The serial stream is shifted out of the first DAC of each pair and into the second DAC. A common latch updates all DACs.

The outputs swing ±10V to provide the Command Output voltage. The reference signal for the Command Output is each individual DAC's analog ground. Each Command Output is capable of driving a load of 10k and 220pF (typical brushless amp input over 6 feet of cable) with a slew rate of 4 V/microsec (20 Volt swing at 20 kHz). See Chapter 3 for specifications on command voltage outputs.


Note	The AD7849BR DAC used on the XMP should not need calibration. The bipolar zero error is specified at ±2 LSBs (0.6 mV) at 25° C. Between -40° C and +85° C, bipolar zero error is ±12 LSBs (3.6 mV). Calibration should not be required. The outputs are fault protected (switched to AGND) for power-on/power-off and emergency conditions.

SERCOS Subsystems

The SERCOS subsystem is an interface between the SHARC processor subsystem and a drive. A drive is generally referred to as a Node. A Node is a SERCOS slave representing a drive, I/O block, etc. A SERCOS subsystem can support up to eight nodes. An XMP-SERCOS controller can support up to four SERCOS subsystems.

The SERCOS subsystem consists of a SERCOS interface and a set of fiber optic transceivers. The fiber optic transceivers allow communication with the SERCOS Nodes via a serial data stream. The SERCOS subsystem supports data streams with rates of 2, 4, or 10 MBaud.

The SERCOS interface is responsible for synchronizing data transmission by transmitting a Master Synchronization Telegram (MST) at a defined interval (Tscyc). Tscyc can be programmed to be a power of 2 of the XMP sample rate.

Each SERCOS subsystem is mapped to a specific location in the SHARC memory space. This allows the SHARC processor to directly access registers and memory in the SERCOS subsystem. This, in turn, allows direct mapping of command and feedback data for each Node. The analog and SERCOS versions of the XMP use the same firmware.

For more information on SERCOS hardware, please refer to Chapter 5.